The S-Parameters intended for simulations are available for the current product spectrum.
The data was generated in CITI file and Touchstone formats.
You will find data
for a capacitor connected in series between port 1 and port 2
and for a parallel circuit (shunt configuration), i.e. the capacitors is connected between lines 1 and 2 of port 1 or port 2, line 2 usually being designated ground (GND)
The data represents the typical behavior of the single component. Special allowance must be made for changes resulting from the environment (through-plated holes, wiring, etc). The S-Parameters do not cover the influence of temperature changes or different voltage ratios at the capacitor. Here the characteristics given in the data sheets apply, to which attention is drawn.
Graphs with impedance graphs can also be downloaded as PDFs. Follow the links below.
The impedance graphs are based on measurements conducted with the Agilent E4991A impedance analyzer. A test voltage of 100 mV without a superimposed DC voltage Vdc was applied during the measurements, which were conducted at a room temperature of 25 °C.
The curves represent the typical behavior of the single component. The influence of temperature changes or different voltage ratios at the capacitor is not covered by the voltage curves. Here the characteristics given in the data sheets apply, to which attention is drawn.
The main application for multilayer ceramic capacitors is the filtering of ripple voltages as they occur in many cases, e.g. phase angle modulated power. Due to their many advantages as low ESR, low impedance, small volume and high reliability, MLCCs are very suitable for AC voltages. However, there are restrictions to the range of the ripple voltage that may be applied to an MLCC. This paper is meant as a guideline for design engineers. It describes the useable range, and the restrictions which must be considered by applying a sinus voltage Vrms. All investigations are based on sinusoidal signals.
